1. Field of the Invention
The invention generally relates to differential signals, and, more particularly, to duty restoration of differential clock signals.
2. Description of the Related Art
Delay locked loops (DLL) are utilized in a wide variety of integrated circuit (IC) devices to synchronize output signals with periodic input signals. In other words, the objective of the DLL is to adjust a phase difference between the input and output signals near zero, for example, to align rising or falling edges of the input and output signals.
FIG. 1 illustrates an exemplary dynamic random access memory (DRAM) device 100 utilizing a delay locked loop (DLL) circuit 110. A typical DRAM specification is that data from memory arrays 104 be available on output lines DQ[0:N] in conjunction with the rising edge (and falling edge in double data rate devices) of an externally supplied clock signal (EXT CLK). In some cases, the DRAM 100 may supply a data strobe signal (DQS) controlled, for example by DQS generator 106. Typically, the DQS signal should also be synchronized with EXT CLK, thus indicating the data is available.
The DLL circuit 110 may be used to synchronize the DQS and DQ signals with the EXT CLK signal through the introduction of an artificial delay of EXT CLK. Thus, the DLL circuit 110 may be used to increase the valid output data window by synchronizing the output of data with both the rising and falling edges of an output clock CLKOUT applied to the driver circuits 108.
As illustrated, the DLL circuit 110 may include duty restoration circuitry 112, phase adjust/delay circuitry 114 (referred to generally as delay circuitry 114), control circuitry 116, and a phase detector 118.
The phase detector 118 may be used to synchronize the externally received clock signal with DQS by comparing the CLKIN signal to a feedback clock signal CLKFB signal using a feedback loop. To synchronize the CLKIN and CLKFB signals, the phase detector 118 may compare the phase of CLKFB to CLKIN and generate a signal to the control circuitry 116. The control circuitry 116 may output control signals to the delay circuitry 114 which may use the control signals to properly align the phases of CLKIN and CLKFB.
The EXT CLK may pass through one or more electrical connections and circuits (e.g., input buffer 102) before being received by the DLL circuit 100 as the CLKIN signal. The DLL circuit 110 may have duty restoration circuitry 112 for restoring a duty cycle of the CLKOUT signal. A duty cycle is the ratio of the on-time of a signal to the period of the signal. Thus, the duty cycle of a signal is the percentage of time that the signal is asserted to a high logic level. To output data accurately from the memory device 100, it may be desired that the CLKOUT signal have a duty cycle of 50%, such that the CLKOUT signal is asserted to a high logic level for half of the CLKOUT period and asserted to a low logic level for the other half of the CLKOUT period.
However, in some cases, the duty cycle of the CLKIN signal may be altered as it passes through the delay circuitry 114 and is output as the CLKOUT signal. For example, the delay circuitry may respond differently to rising and falling edges of the clock signals, such that the rise time (tRISE) of a signal passing through the circuit does not equal the fall time (tFALL) of a signal passing through the circuit. As a result, the rising and falling edges of the signals may be delayed by differing amounts. Thus, the duty restoration circuitry 112 may be used to restore the duty cycle of the CLKOUT signal.
As depicted, the clock signals CLKIN, CLKOUT, and CLKFB may all be signals which are delivered on a single line. In some cases, signals delivered on a single line may be subject to noise from other nearby lines (referred to as cross-talk), from noise in driver circuitry used to drive the signals, or from other sources, such as fluctuations in a power supply used to drive the signal. Because such signals are typically measured as absolute voltages with respect to a ground voltage, noise may distort the signals and cause the signals to be read incorrectly. In a low power, high speed memory device, such noise may limit performance of the memory device.
To overcome the performance limitations caused by signal noise, complementary signal pairs (also referred to as differential signal pairs) may be utilized by the memory device 100. A complementary signal pair is a signal and its complement (i.e., a signal and the inverse of the signal). Complementary signals may have greater immunity to noise than normal signals because a complementary signal is measured by determining a difference between two voltages (the signal and its complement). If the measured difference is positive, the signal is positive, and if the measure difference is negative, the signal is negative. Because both the signal and its complement are presumably affected in the same manner by noise in the circuit (e.g., both signals are distorted by a like amount), the noise in the complementary signal pair will cancel when the signal and its complement are compared relative to each other.
Thus, by using complementary signals for CLKIN, CLKOUT, and CLKFB, the performance of the memory device 100 may be improved. However, as described above, the duty cycle of the clock signals may be distorted by circuitry in the memory device 100, such as the delay circuitry 114. While the duty restoration circuitry 112 described above may be used to restore the duty cycle of a single clock signal, conventional duty restoration circuits are limited to single-ended signals and are not used in restoring complementary signal pairs.
Accordingly, what is needed are methods and circuits for restoring the duty cycle of a complementary signal pair.